The present invention relates generally to semiconductor manufacturing, and more particularly to a method for manufacturing a phase change memory device with roundless micro-trenches.
Phase change memory is a type of non-volatile memory that uses two distinct phases of its material components to represent binary logic states. Study has shown that chalcogenic materials, such as Ge—Sb—Te-based materials, in an amorphous phase have a distinctively higher resistance than that of a crystalline phase. The crystalline phase can be obtained by raising the temperature of the chalcogenic materials above approximately 200 degrees Celsius, and maintaining it for a sufficient amount of time. The amorphous phase can be obtained by raising the temperature of the chalcogenic materials above their melting points of approximately 600 degrees Celsius, and cooling it off rapidly.
The phase change memory has certain advantages over conventional flash memory, which recognizes binary logic states by the existence or non-existence of electrons tunneling through a barrier layer into a charge trapping layer. Current leakage and tunnel barrier failure are often observed in such conventional flash memory design that requires a charge trapping layer, thereby inducing reliability issues. By using the phases of crystallization to represent logic states, the phase change memory eliminates the need of the charge trapping layer, and therefore is free from the current leakage and tunnel barrier failure issues. Moreover, the phase change memory offers much faster programming speed than the flash memory as it requires a long period of time for its charge pump to build up sufficient power for the tunneling effect to take place. Thus, the phase change memory has become one of the promising candidates for the next generation memory.
One of the challenges facing the development of the phase change memory is to reduce its power consumption, which can be quite high due to the power required to heat up the chalcogenic materials in changing their crystallization during each programming cycle. One solution of reducing the power consumption of the phase change memory is to lower its reset current level. In order to lower the reset current level, the area of the bottom electrode of the phase change memory needs to be reduced accordingly.
As such, it is desired to design a phase change memory device with reduced area of bottom electrodes in order to reduce it power consumption.